//Original:/proj/frio/dv/testcases/core/c_dsp32alu_rrpmmp_sft_x/c_dsp32alu_rrpmmp_sft_x.dsp
// Spec Reference: dsp32alu (dreg, dreg) = +/-, -/+ (dreg, dreg) >>, <<
# mach: bfin

.include "testutils.inc"
	start

	R0 = 0;
	ASTAT = R0;

	imm32 r0, 0x35678911;
	imm32 r1, 0x2489ab1d;
	imm32 r2, 0x34545515;
	imm32 r3, 0x46667717;
	imm32 r0, 0x5567891b;
	imm32 r1, 0x67889b1d;
	imm32 r2, 0x74445915;
	imm32 r3, 0x86667797;
	R0 = R0 +|- R0 , R7 = R0 -|+ R0 (CO , ASR);
	R1 = R0 +|- R1 , R6 = R0 -|+ R1 (CO , ASR);
	R2 = R0 +|- R2 , R5 = R0 -|+ R2 (CO , ASR);
	R3 = R0 +|- R3 , R4 = R0 -|+ R3 (CO , ASR);
	R4 = R0 +|- R4 , R3 = R0 -|+ R4 (CO , ASR);
	R5 = R0 +|- R5 , R2 = R0 -|+ R5 (CO , ASR);
	R6 = R0 +|- R6 , R1 = R0 -|+ R6 (CO , ASR);
	R7 = R0 +|- R7 , R0 = R0 -|+ R7 (CO , ASR);
	CHECKREG r0, 0x00006626;
	CHECKREG r1, 0xfb7743ec;
	CHECKREG r2, 0xf848146e;
	CHECKREG r3, 0x33c00cce;
	CHECKREG r4, 0x4899cc40;
	CHECKREG r5, 0x40f807b7;
	CHECKREG r6, 0x117a0488;
	CHECKREG r7, 0xef410000;

	imm32 r0, 0xe5678911;
	imm32 r1, 0x2e89ab1d;
	imm32 r2, 0x34e45515;
	imm32 r3, 0x466e7717;
	imm32 r0, 0x5567ee1b;
	imm32 r1, 0x6789abed;
	imm32 r2, 0x7444551e;
	imm32 r3, 0x86e67777;
	R0 = R1 +|- R0 , R7 = R1 -|+ R0 (CO , ASR);
	R1 = R1 +|- R1 , R6 = R1 -|+ R1 (CO , ASR);
	R2 = R1 +|- R2 , R5 = R1 -|+ R2 (CO , ASR);
	R3 = R1 +|- R3 , R4 = R1 -|+ R3 (CO , ASR);
	R4 = R1 +|- R4 , R3 = R1 -|+ R4 (CO , ASR);
	R5 = R1 +|- R5 , R2 = R1 -|+ R5 (CO , ASR);
	R6 = R1 +|- R6 , R1 = R1 -|+ R6 (CO , ASR);
	R7 = R1 +|- R7 , R0 = R1 -|+ R7 (CO , ASR);
	CHECKREG r0, 0x336f197e;
	CHECKREG r1, 0x00005dce;
	CHECKREG r2, 0xfcd11e7d;
	CHECKREG r3, 0x382815e7;
	CHECKREG r4, 0x51a2c7d7;
	CHECKREG r5, 0x490c032f;
	CHECKREG r6, 0x09bb0000;
	CHECKREG r7, 0xe6822a5e;

	imm32 r0, 0x15678911;
	imm32 r1, 0x2789ab1d;
	imm32 r2, 0x34445515;
	imm32 r3, 0x46667717;
	imm32 r0, 0x5567891b;
	imm32 r1, 0x6789ab1d;
	imm32 r2, 0x74445515;
	imm32 r3, 0x86667777;
	R0 = R2 +|- R0 , R7 = R2 -|+ R0 (CO , ASR);
	R1 = R2 +|- R1 , R6 = R2 -|+ R1 (CO , ASR);
	R2 = R2 +|- R2 , R5 = R2 -|+ R2 (CO , ASR);
	R3 = R2 +|- R3 , R4 = R2 -|+ R3 (CO , ASR);
	R4 = R2 +|- R4 , R3 = R2 -|+ R4 (CO , ASR);
	R5 = R2 +|- R5 , R2 = R2 -|+ R5 (CO , ASR);
	R6 = R2 +|- R6 , R1 = R2 -|+ R6 (CO , ASR);
	R7 = R2 +|- R7 , R0 = R2 -|+ R7 (CO , ASR);
	CHECKREG r0, 0x0f820874;
	CHECKREG r1, 0x0afafff3;
	CHECKREG r2, 0x00000f97;
	CHECKREG r3, 0x3b771c44;
	CHECKREG r4, 0x57ffc488;
	CHECKREG r5, 0x64ac0000;
	CHECKREG r6, 0x000c049d;
	CHECKREG r7, 0xf78c0014;

	imm32 r0, 0x85678911;
	imm32 r1, 0x2889ab1d;
	imm32 r2, 0x34445515;
	imm32 r3, 0x46667717;
	imm32 r0, 0x5587891b;
	imm32 r1, 0x6788ab1d;
	imm32 r2, 0x74448515;
	imm32 r3, 0x86667877;
	R0 = R3 +|- R0 , R7 = R3 -|+ R0 (CO , ASR);
	R1 = R3 +|- R1 , R6 = R3 -|+ R1 (CO , ASR);
	R2 = R3 +|- R2 , R5 = R3 -|+ R2 (CO , ASR);
	R3 = R3 +|- R3 , R4 = R3 -|+ R3 (CO , ASR);
	R4 = R3 +|- R4 , R3 = R3 -|+ R4 (CO , ASR);
	R5 = R3 +|- R5 , R2 = R3 -|+ R5 (CO , ASR);
	R6 = R3 +|- R6 , R1 = R3 -|+ R6 (CO , ASR);
	R7 = R3 +|- R7 , R0 = R3 -|+ R7 (CO , ASR);
	CHECKREG r0, 0x8fb3ff9b;
	CHECKREG r1, 0x8b33f71b;
	CHECKREG r2, 0x8804009d;
	CHECKREG r3, 0x000086f7;
	CHECKREG r4, 0xff6e0000;
	CHECKREG r5, 0xff63fef3;
	CHECKREG r6, 0x08e5fbc4;
	CHECKREG r7, 0x0064f744;

	imm32 r0, 0x15678911;
	imm32 r1, 0x2789ab1d;
	imm32 r2, 0x34445515;
	imm32 r3, 0x46667717;
	imm32 r0, 0x5567891b;
	imm32 r1, 0x6789ab1d;
	imm32 r2, 0x74445515;
	imm32 r3, 0x86667777;
	R0 = R4 +|- R0 , R7 = R4 -|+ R0 (CO , ASR);
	R1 = R4 +|- R1 , R6 = R4 -|+ R1 (CO , ASR);
	R2 = R4 +|- R2 , R5 = R4 -|+ R2 (CO , ASR);
	R3 = R4 +|- R3 , R4 = R4 -|+ R3 (CO , ASR);
	R4 = R4 +|- R4 , R3 = R4 -|+ R4 (CO , ASR);
	R5 = R4 +|- R5 , R2 = R4 -|+ R5 (CO , ASR);
	R6 = R4 +|- R6 , R1 = R4 -|+ R6 (CO , ASR);
	R7 = R4 +|- R7 , R0 = R4 -|+ R7 (CO , ASR);
	CHECKREG r0, 0xEA813B97;
	CHECKREG r1, 0xE5F93316;
	CHECKREG r2, 0xe2ca0898;
	CHECKREG r3, 0x3C840000;
	CHECKREG r4, 0x3BBB0000;
	CHECKREG r5, 0x33221D35;
	CHECKREG r6, 0x08A41A07;
	CHECKREG r7, 0x0024157E;

	imm32 r0, 0x95678911;
	imm32 r1, 0x2789ab1d;
	imm32 r2, 0x39445515;
	imm32 r3, 0x46967717;
	imm32 r0, 0x5567891b;
	imm32 r1, 0x6789ab1d;
	imm32 r2, 0x74495515;
	imm32 r3, 0x86669777;
	R0 = R5 +|- R0 , R7 = R5 -|+ R0 (CO , ASR);
	R1 = R5 +|- R1 , R6 = R5 -|+ R1 (CO , ASL);
	R2 = R5 +|- R2 , R5 = R5 -|+ R2 (CO , ASR);
	R3 = R5 +|- R3 , R4 = R5 -|+ R3 (CO , ASL);
	R4 = R5 +|- R4 , R3 = R5 -|+ R4 (CO , ASR);
	R5 = R5 +|- R5 , R2 = R5 -|+ R5 (CO , ASR);
	R6 = R5 +|- R6 , R1 = R5 -|+ R6 (CO , ASR);
	R7 = R5 +|- R7 , R0 = R5 -|+ R7 (CO , ASL);
	CHECKREG r0, 0xDDBACBFA;
	CHECKREG r1, 0xCB995440;
	CHECKREG r2, 0xDF6C0000;
	CHECKREG r3, 0x227525AF;
	CHECKREG r4, 0x1375bCF7;
	CHECKREG r5, 0x39250000;
	CHECKREG r6, 0xE4E43467;
	CHECKREG r7, 0x189A2246;

	imm32 r0, 0x15678911;
	imm32 r1, 0x2789ab1d;
	imm32 r2, 0x34445515;
	imm32 r3, 0x46667717;
	imm32 r0, 0x5567891b;
	imm32 r1, 0x6789ab1d;
	imm32 r2, 0x74445515;
	imm32 r3, 0x86667777;
	R0 = R6 +|- R0 , R7 = R6 -|+ R0 (CO , ASR);
	R1 = R6 +|- R1 , R6 = R6 -|+ R1 (CO , ASL);
	R2 = R6 +|- R2 , R5 = R6 -|+ R2 (CO , ASL);
	R3 = R6 +|- R3 , R4 = R6 -|+ R3 (CO , ASR);
	R4 = R6 +|- R4 , R3 = R6 -|+ R4 (CO , ASR);
	R5 = R6 +|- R5 , R2 = R6 -|+ R5 (CO , ASR);
	R6 = R6 +|- R6 , R1 = R6 -|+ R6 (CO , ASL);
	R7 = R6 +|- R7 , R0 = R6 -|+ R7 (CO , ASR);
	CHECKREG r0, 0xE3DF0EAF;
	CHECKREG r1, 0xEAD80000;
	CHECKREG r2, 0xC81F0FB9;
	CHECKREG r3, 0x0B83C2F9;
	CHECKREG r4, 0xFC0FEF32;
	CHECKREG r5, 0xaF4F3297;
	CHECKREG r6, 0xFC200000;
	CHECKREG r7, 0xED701C21;

	imm32 r0, 0x67898911;
	imm32 r1, 0xb789ab1d;
	imm32 r2, 0x3b445515;
	imm32 r3, 0x46b67717;
	imm32 r0, 0x5567891b;
	imm32 r1, 0x678bab1d;
	imm32 r2, 0x7444b515;
	imm32 r3, 0x86667b77;
	R0 = R7 +|- R0 , R7 = R7 -|+ R0 (CO , ASR);
	R1 = R7 +|- R1 , R6 = R7 -|+ R1 (CO , ASR);
	R2 = R7 +|- R2 , R5 = R7 -|+ R2 (CO , ASL);
	R3 = R7 +|- R3 , R4 = R7 -|+ R3 (CO , ASR);
	R4 = R7 +|- R4 , R3 = R7 -|+ R4 (CO , ASL);
	R5 = R7 +|- R5 , R2 = R7 -|+ R5 (CO , ASL);
	R6 = R7 +|- R6 , R1 = R7 -|+ R6 (CO , ASL);
	R7 = R7 +|- R7 , R0 = R7 -|+ R7 (CO , ASR);
	CHECKREG r0, 0xCC040000;
	CHECKREG r1, 0x031A2E1C;
	CHECKREG r2, 0x1170A0D8;
	CHECKREG r3, 0xE4405DC2;
	CHECKREG r4, 0xECB64BD0;
	CHECKREG r5, 0xA9A01EA0;
	CHECKREG r6, 0x1C5C2CF6;
	CHECKREG r7, 0xD29E0000;

	imm32 r0, 0xe5678911;
	imm32 r1, 0x2e89ab1d;
	imm32 r2, 0x34ee5515;
	imm32 r3, 0x4666e717;
	imm32 r0, 0x5567891b;
	imm32 r1, 0x6789ae1d;
	imm32 r2, 0x744455e5;
	imm32 r3, 0x8666777e;
	R4 = R2 +|- R5 , R3 = R2 -|+ R5 (CO , ASR);
	R0 = R5 +|- R3 , R5 = R5 -|+ R3 (CO , ASL);
	R2 = R6 +|- R2 , R0 = R6 -|+ R2 (CO , ASR);
	R3 = R4 +|- R0 , R2 = R4 -|+ R0 (CO , ASR);
	R7 = R7 +|- R6 , R6 = R7 -|+ R6 (CO , ASR);
	R6 = R1 +|- R7 , R1 = R1 -|+ R7 (CO , ASL);
	R5 = R0 +|- R4 , R7 = R0 -|+ R4 (CO , ASR);
	R1 = R3 +|- R1 , R4 = R3 -|+ R1 (CO , ASL);
	CHECKREG r0, 0x416dd40c;
	CHECKREG r1, 0xaEE68766;
	CHECKREG r2, 0xF7D7e6C2;
	CHECKREG r3, 0x282F23CB;
	CHECKREG r4, 0x07C6f1D6;
	CHECKREG r5, 0x282FDC35;
	CHECKREG r6, 0xBE0C8930;
	CHECKREG r7, 0xF7D7193D;

	imm32 r0, 0xff678911;
	imm32 r1, 0x2789ab1d;
	imm32 r2, 0x3f445515;
	imm32 r3, 0x46f67717;
	imm32 r0, 0x556f891b;
	imm32 r1, 0x6789fb1d;
	imm32 r2, 0x74445f15;
	imm32 r3, 0x866677f7;
	R4 = R3 +|- R3 , R5 = R3 -|+ R3 (CO , ASR);
	R1 = R6 +|- R1 , R6 = R6 -|+ R1 (CO , ASL);
	R6 = R1 +|- R4 , R4 = R1 -|+ R4 (CO , ASR);
	R7 = R4 +|- R2 , R0 = R4 -|+ R2 (CO , ASL);
	R2 = R2 +|- R6 , R1 = R2 -|+ R6 (CO , ASR);
	R3 = R5 +|- R5 , R7 = R5 -|+ R5 (CO , ASL);
	R5 = R7 +|- R7 , R3 = R7 -|+ R7 (CO , ASR);
	R0 = R0 +|- R0 , R2 = R0 -|+ R0 (CO , ASR);
	CHECKREG r0, 0x82EE0000;
	CHECKREG r1, 0x369445BE;
	CHECKREG r2, 0x339E0000;
	CHECKREG r3, 0x00000000;
	CHECKREG r4, 0x0E136262;
	CHECKREG r5, 0x00000000;
	CHECKREG r6, 0xe8C80E13;
	CHECKREG r7, 0x00000000;

	pass
